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Apple Expected to Use TSMC's Advanced 5nm+ and 4nm Technologies for Future iPhone Chips, Likely Macs Too
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Seems like GAAFET (Gate All-Around FETs) are the answer at below 5 nm. Pretty interesting transistor design - utilizing carbon nanowires with the gate wrapping around them.
Very important, yes. Exciting, also yes. But revolutionary? Perhaps down the line, but so far EUV has just allowed these fabs to make pretty minor, incremental, evolutionary improvements. I guess they all add up over 5-10 years, though! TSMC must own over half the EUV ASML machines in existence at this point.
The node shrink (TSMC's 5 nm EUV process) is really the major driver here - it's the first commercial EUV lithography produced chip (though there was a Kirin chip made with 7 nm EUV before). Apple's architecture is obviously amazing too, but it's really the breakthrough of Extreme Ultraviolet Lithography led by ASML that accounts for the A14 & M1's prowess.
Could be. Or MBCFET. Or any of a large number of other choices that all operate on the same principle of applying the electrical field to gate from more directions. Not sure 4nm is where they have to do it, but they’ll need to do it before 2030 probably.
Revolutionary, yes. Shrinking the light source from 193 nm to 13.5 nm is a gargantuan step. To produce at 10 nm, upto quadruple patterning (with multiple litho-etch steps) was used. EUV simplifies this process tremendously, and on N5, a lot more layers of EUV are being used. It's the biggest improvement in lithography we've seen yet, 5 nm simply would not be possible without it.
I've also heard rumors that after the new spring announcements next year, we'll see summer.
Here is the timeline released my TSMC themselves.
And the performance and battery life increases are stunning. I think I'll wait for the M3. When Apple says the transition will be over in 2 years, this is what they mean:
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Very exciting! The jump from N5 to N3 will be massively significant. I believe it will primarily depend on ASML's new high-NA EXE 5000 system, which will allow for smaller patterns to be resolved. TSMC has been very aggressive with EUV implementation, and it shows. Intel and Globalfoundries have all but given up on EUV, and seem to have let DUV play its course. Fabs simply cannot ramp up fast enough to accommodate 5 nm for all vendors - it takes a couple years to tool for EUV, and ASML's order book is backed up quite a bit.
Here is the timeline released my TSMC themselves.
And the performance and battery life increases are stunning. I think I'll wait for the M3. When Apple says the transition will be over in 2 years, this is what they mean:
TSMC is also expanding, building a fab in Arizona. Samsung is also aggressively starting to use EUV for memory as well as logic (there was a new Exynos chip they launched very recently that uses EUVL).
That would be physically impossible as the size of an atom of silicon is .2nm. But we can surely see some wafers which are less than 3nm. You would have to move on to another element, or go quantum.
I am not going to pretend that I understand any of what you said, but I appreciate that
Remember too that 5nm doesn’t mean any gates are actually 5nm wide. The node names have different meanings at different fabs, but usually they are somewhat correlated with the smallest possible feature size, and transistor gates are bigger than that.
I keep hearing people excited that Apple will push performance boundaries because of TSMC and to expect huge increases year over year (not a critique of you, i've been seeing this in comments and in youtube).... it makes me cringe. If I had to predict (and I may be wrong), we just saw the biggest year-over-year jump because they kicked Intel to the curb and went to a new architecture that is just much more efficient. Obviously, it will scale somewhat linearly (to a point) by throwing more cores for higher end machines, and obviously they will evolve their core design over time and target new processes. But I think some are being super unreasonable when they throw massive % performance improvements between generations in the future.
Don't get me wrong... I think M1 is impressive, and I think the line will continue to be impressive... and I think for a few years they will improve performance at a faster pace than Intel has been... I just don't think they will work miracles - that they have bought extra runway in the fight against physics, and people should level set their expectations.
It will be interesting to see how much further TSMC can push their process innovations before their pace slows down, or if the cost starts becoming prohibitive for consumer components. There is lots of interesting research going on that i've read up in recent times - none of which I'm really qualified to fully understand at all, but many things just don't have a way to scale to producing billions of transistors in a timely manner and without massive defect rates at the moment. I find it hard to believe in 10 years many of those will be in production.
The one thing TSMC did right, which Intel didn't, is they went one step at a time. Intel tried to debut a whole bunch of new technologies in a single process node, and they just cratered. TSMC has been introducing changes more frequently but independently. Assuming Intel doesn't get out of the fab business after all of this, I would really hope they've learned some good lessons out of this fiasco.
TSMC has timetable for 3nm process and are planning for 2nm plant in northern Taiwan. However I do wonder when they will stop counting by nm. Maybe we will use number of atoms instead for the future.
TSMC to build 2nm wafer plant in Hsinchu - Focus Taiwan
Taipei, Sept. 23 (CNA) Taiwan Semiconductor Manufacturing Co. (TSMC), the world's largest contract chipmaker, said Wednesday it will build a sophisticated 2 nanometer wafer plant in Hsinchu.
TSMC has timetable for 3nm process and are planning for 2nm plant in northern Taiwan. However I do wonder when they will stop counting by nm. Maybe we will use number of atoms instead for the future.
TSMC to build 2nm wafer plant in Hsinchu - Focus Taiwan
Taipei, Sept. 23 (CNA) Taiwan Semiconductor Manufacturing Co. (TSMC), the world's largest contract chipmaker, said Wednesday it will build a sophisticated 2 nanometer wafer plant in Hsinchu.focustaiwan.tw
They used to use microns. Nothing magical about nanometers. Next will be angstroms.
It’s not a matter of the name of the process. And “5nm” is just a name, it’s not the size of the transistor gate. They can get quite a bit smaller before they get stuck. Changing the gate structure so that the electric field can be applied from all sides will help.
We already worry about quantum effects - we have been dealing with them for at least 10 years. It’s part of why we have static leakage current even when devices are shut off.
According to this article, Samsung will gate-all-around in 2022 for their 3nm process & TSMC will adopt the same in 2024
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GAA is what Samsung & TSMC will relying on starting in 2022 & 2024 respectively.
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I don't have a good picture of what transistors look like, so I found this simplified cartoon, pasted below, at https://semiengineering.com/transistor-options-beyond-3nm/
Is the "gate" in these pictures the active semiconductor device itself, i.e., the object that is switched between conducting and non-conducting states? If so, how thick are the gates in TSMC's 5 nm process (or their thickness range, if they vary)? How would Intel's 14 nm process compare in this respect? When someone refers to "gate size", are they referring to its thickness?
By my calculation, there are 3.683 silicon atoms/nm in an undoped silicon crystal.
And is there generally a linear relationship between a company's marketing label for the process size and the gate thickness?
E.g., is the gate thickness for Intel's 14 nm process (about) half that for their 28 nm process?
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