dumped mine at 89. took almost a year to go from 50ish to current. way too slow of growth.
Got a tip for us?
Let us know
Become a MacRumors Supporter for $50/year with no ads, ability to filter front page stories, and private forums.
Apple Expected to Use TSMC's Advanced 5nm+ and 4nm Technologies for Future iPhone Chips, Likely Macs Too
- Thread starter MacRumors
- Start date
- Sort by reaction score
Ankers 30w charger is 2x the size or Apple's 5w but still impressive. And it's not 100% GaN
The “gate size” is what we call the “length” of the gate, though the way these are drawn it’s a little confusing. If you look at the planar transistor, you have a source, a gate, and the a drain. The gate length is the dimension between the two yellow things. In transistors, what matters most is the ratio between the width and the length - a high width-to-length ratio allows you to drive higher currents, and switch more quickly for a given capacitive load. But a high gate width means a high capacitance is added to whatever transistor is driving the gate. So there are trade offs. But the gate length is almost never “5nm” on a 5nm process. It’s almost always bigger, for lots of reasons.
The gate length also does not necessarily scale linearly to the ”process size.” It depends on the fab, but often times you shrink by a lot less than the “process” nominally does.
The gate is the portion of the device that is turned on and off to allow current to flow from the drain to the source (or source to the drain, depending on whether you prefer to think of current as flowing electrons or holes).
By applying a voltage between the gate and source, you can create an electric field which extends into the region under the gate (in the planar transistor). The electric field repels carriers of one type and attracts carriers of the opposite polarity (which is which depends on whether it’s a pfet or an nfet), and creates a conducting region under the gate between the source and the drain.
But the field, in this case, is driven from above, and has to extend down into the substrate, where the current flows. In the FINFET, you have a 3D source and drain. When you apply a voltage to the gate, the electric field surrounds the current-carrying channels from more directions, allowing it to more completely be shut off. (We are usually worried about shutting OFF the channel more so than turning it on)
GaN isn’t well-suited to high density digital circuitry. It has good power density which makes it good for things like chargers, and good switching speed which makes it good for discrete transistors, but I would expect that the SiGe would be next, followed by GaAs, which has already been successfully used to make CPUs.
Remember, too, that even with Si, there are other types of transistors and other types of circuits that could be used to increase speed without having to switch materials systems.
I suspect that at some point in the not too distant future Intel will realize they lost the race on the manufacturing side, and switch strategy: x86 using TSMC manufacturing processes would be a big step forward already, and the gap is only getting bigger. I think this is going to be Intel’s response, but likely too late because they will not do it before they have no other choice, unless they prefer to close up shop.
That's a very aggressive timeline from Samsung and I don't believe a word of it (the timeline).According to this article, Samsung will gate-all-around in 2022 for their 3nm process & TSMC will adopt the same in 2024
BNN Bloomberg - Canada Business News, TSX Today, Oil and Energy Prices
Get the latest Canadian business news, including TSX updates, changes to oil and energy prices, and Bank of Canada coverage. Explore stock market investing and get expert financial insights on investment portfolio strategies.www.bnnbloomberg.ca
Their 5nm node that for example the Snapdragon 875 will use (2021) is closer in density to TSMC's latest generation 7nm node than to TSMC's current 5nm node.
TSMC's 5nm node is 37% more dense than Samsung's 5nm node. Catching up with marketing names like "5nm", "4nm", "3nm" doesn't mean they're catching up in actual technology where TSMC has a huge lead.
Thanks! So, effectively, the gate length is the distance the current needs to traverse through the semiconductor when the gate is on, and the thickness of the insulation present when the gate is off. Thus it's this thickness (and the nature of the material itself) that determines the extent to which other technologies need to be applied to reduce quantum tunneling. Is that essentially correct?
Now that I know "gate length" is the proper term of art, I was able to do some searches to determine what the gate lengths actually are. For current 5 nm processes, gate length appears to be ~10–15 nm, which means they're ~37–55 silicon atoms thick. Remarkable.
I also learned that, initially, the node size actually meant the gate length, until the two diverged for marketing reasons: (source: Kevin Morris, https://www.eejournal.com/article/no-more-nanometers/):
Last edited:
Jesus, Intel just cannot catch a break.
Because, once they solve one problem, they run into another. It's not just the gate sizes, but the manufacturing process. This is the big issue with Intel - from what I understand - is that their 7nm lithography technology just isn't getting good yields. So, not only do you have to overcome the physics but also the manufacturing of the chips. Sure, you can design chips, but then there are the material properties needed, and the cost effectiveness.
Every year there's a new wall, because there's always a new challenge to overcome.
I can't fathom how small we're getting. Under 5nm is crazy and I can't imagine seeing anything like that in the next 2-4 years.
It will likely not be correct. Firestorm is the code name of the performance cores of the A14 generation (and therefore M1). You would expect the M2 to be the same generation as the A15 and have new core designs with new code names.
Xi will believe, correctly in my opinion, that Western countries won’t dare to confront China when they swallow Taiwan just like they are doing nothing to help Hong Kong but that is not a purpose of the discussion in this thread so I won’t comment about it further.
Correct I shouldn’t have gone into PRSI I will edit it.
I will say I hope we have more resolve than that. If not we won the Cold War and then rolled over for no reason. The United Kingdom is extending citizenship for many in Hong Kong if they want to avoid the CPC, it’s the best they can do without a war.
Last edited:
TSMC and Apple could move to the denser smaller node right now, but they want to milk the cow… That is why Intel is also stuck in 10 nm firings their feet. But eventually, the node limit will be reached. How many steps in node reduction until Silicon reaches its quantum mechanics limits? 5 nm - 4 nn - 3 nm - 2 nm - 1 nm? And what after that? Thanks.
And to think some of my friends were absolutely chuffed and happy with the 6 before they passed.
Life is truly amazing. We will always progress . By the time silicons limits are reached we will have a new platform. If history has taught us anything it’s to never expect humans to simply stagnate.