I do, we have them as a client.
We hear a lot of bragging here on MR for stuff made in the USA, guess what, they'd be nowhere without foreign tech (and foreigners) including ASML/Arm/Samung amongst many..MANY others.
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Apple Expected to Use TSMC's Advanced 5nm+ and 4nm Technologies for Future iPhone Chips, Likely Macs Too
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We hear a lot of bragging here on MR for stuff made in the USA, guess what, they'd be nowhere without foreign tech (and foreigners) including ASML/Arm/Samung amongst many..MANY others.
I do, we have them as a client.
We hear a lot of bragging here on MR for stuff made in the USA, guess what, they'd be nowhere without foreign tech (and foreigners) including ASML/Arm/Samung amongst many..MANY others.
FWIW, Apple doesn't use much of anything from ARM other than the ISA. And the mac would be just as fast if they used RISC-V, powerpc, or something they invented themselves. Someday they might
(They've started down that road)
=1000 picometer
I know..I know, zero is zero, but many people here ask what after 1 nm, what do we get, wel, picometers.
0.2 nanometer =120 picometer
It's pointless to look too far ahead; too little is certain. BUT
- transistors can get somewhat smaller (3nm)
- transistor performance can still increase somewhat (GAA)
- a CMOS "transistor" consists of two transistors, N and P. These can be stacked on top of each other instead of side by side.
- already in some situations the fundamental limit is no longer transistor size but the density of the wiring connecting to the transistors. This can be substantially helped by routing the "utility" connections (at first power/ground, later maybe clock) below the transistors rather than above
- chip elements can be stacked vertically. Yes that means you have to be careful with heat dissipation. Would be nice to be prepared for this by having a set of very low power designs ready... (Meanwhile sucks to be AMD or Intel and have bet on high frequency...)
All of these are pretty much already lined up in the pipeline, in various stages of R&D. Orthogonal to all of them, one can imagine using new post-Silicon materials. This has been talked about in various forms since the 80s (and still hasn't happened) because it would be a massively expensive change. My guess is it will happen when there's absolutely no cheaper improvement route left, but not until then.
I think that's unfair.FWIW, Apple doesn't use much of anything from ARM other than the ISA. And the mac would be just as fast if they used RISC-V, powerpc, or something they invented themselves. Someday they might
First of all creating a decent ISA is more difficult (and IMHO more important) than people realize. Intel created many, all of which sucked. RISC-V sucks. POWER was OK for its late 80's timeframe but has aged sub-optimally.
Second there's a bunch of behind-the-scenes glue standard ARM stuff that I'm guessing Apple probably uses, like the buses and coherency protocols. They could have rolled all this stuff themselves, but the ARM stuff is pretty good, and using it means it's just so much easier to interact with any other IP they might want to buy and add to their SoCs.
Third they're probably using a bunch of M0s in the usual places you use things like M0s. They used, eg, an M3 for the motion coprocessor on the A7. My guess is that M0 is optimized enough there's no reason for Apple to spin their own equivalent. M3 (and the motion coprocessor)? Who knows? They have their own tiny 64-bit core (which we never hear of, smaller than the efficiency cores, but with things like PAC) used as a controller for things like the GPU and NPU. Perhaps the motion coprocessor is one of those, though seems like overkill.
I’m quite sure they aren’t using Arm’s buses, fwiw. Might they be using M0s? I dunno. Maybe. Speculation. We know that the Arm cores they put in things like their cables are full custom.
And as someone who designed part of an ISA that most laptops and desktops in the world are currently using, I wouldn’t agree that it’s all that difficult. I also don’t see any significant advantages of Arm over Power (having also designed PowerPC chips, but not Arm chips, so maybe I’m missing something).
Darth Tulhu
macrumors 68020
This is all VERY technical and interesting.
However, I'm still buzzing with excitement at the M1.
I feel the same as when I first saw a Mac with OS X, the table lamp iMac, the original cube, the iPod, and the freaking mind-blowing iPhone!
Things may get better from here, but this is so much more incredible than the typical 1st-gen device.
It's a Back to the Future moment for me, when Marty first hears the words: "Roads? Where we're going we don't need roads".
However, I'm still buzzing with excitement at the M1.
I feel the same as when I first saw a Mac with OS X, the table lamp iMac, the original cube, the iPod, and the freaking mind-blowing iPhone!
Things may get better from here, but this is so much more incredible than the typical 1st-gen device.
It's a Back to the Future moment for me, when Marty first hears the words: "Roads? Where we're going we don't need roads".
A cmos transistor does not consist of two transistors. A cmos inverter does. Or a pass gate. Many cmos gates do not have an equal number of nfets and pfets.
And physically stacking them may be possible some day, but there are thermal issues that prevent it right now. Also, you wouldn’t stack them. You’d probably stack independent circuits.
Sounds like iMac will be before that. Could be that WWDC is iMac Pro/16” MBP/14” MBP, though.
Witeken is notoriously, uh, enthusiastic. But what I said is real, as is this work by Intel. IMEC have also been doing the same sort of thing, for two years now.
If you want to quibble about how I phrased the stacking of N and P transistors, whatever.
Ok. Just so you’re clear that this stacked ribbon thing is somebody making a PFET and an NFET stacked, and you understand that this is not how CMOS circuits work.
For example, here’s a CMOS NOR gate. The transistors with bubbles are PFETS. The ones without are NFETS. Each transistor has its own connections and the channel-connections are logically in a line, but physically stacking these wouldn’t make any sense - you’d have a three-high stack with a mess of wires, and your power plane would be dipping up and down creating all sorts of issues.
And that’s one of the simple CMOS gates.
The thing you posted may make sense for something like pass-transistor logic, but couldn’t be used for CMOS.
(And, of course, a transistor is a transistor, not two transistors, but whatever.)
Well, whom should I trust?
The ARM Fellow writing this blog post:
https://community.arm.com/developer/research/b/articles/posts/three-dimensions-in-3dic---part-iii
or some internet rando?
Decisions, decisions.
Except the thing you cited supports what I said, not what you said. He shows something called a “CFET.” That’s very different than CMOS, which is what you argued. And he doesn’t claim that one CMOS transistor contains two transistors, which you claimed.
He *also* says this would be useful for an *inverter* (which is what I said in my first response to you - the only CMOS logic gate with two transistors - one P and one N - is the inverter). He also suggests it could be used in SRAM bit cells, which is true. He did not mention pass gates, which I did mention. But other than the inverter, none of this is CMOS. And using this for inverters and static RAM wouldn’t be that helpful because a chip is a lot more than inverters and static RAM. Like I said, you would have to use some sort of passgate logic to make this make any sense.
And if we want to compare publications, here’s one of mine, specifically chosen due to its relevance to the Apple community - also, unlike this Arm article you cited, mine was peer-reviewed:
A 533-MHz BiCMOS superscalar RISC microprocessor
This 533-MHz BiCMOS very large scale integration (VLSI) implementation of the PowerPC architecture contains three pipelines and a large on-chip secondary cache to achieve a peak performance of 1600 MIPS. The 15 mm/spl times/10 mm die contains 2.7 M transistors (2M CMOS and 0.7 M bipolar) and...
(Some more at this link: https://ieeexplore.ieee.org/author/37341628900)
That would be great. Already have the 16" MBP so not looking into upgrading my laptop.
I could use an iMac though. Also very interested in their high end M chips.
OFFS.Except the thing you cited supports what I said, not what you said. He shows something called a “CFET.” That’s very different than CMOS, which is what you argued. And he doesn’t claim that one CMOS transistor contains two transistors, which you claimed.
He *also* says this would be useful for an *inverter* (which is what I said in my first response to you - the only CMOS logic gate with two transistors - one P and one N - is the inverter). He also suggests it could be used in SRAM bit cells, which is true. He did not mention pass gates, which I did mention. But other than the inverter, none of this is CMOS. And using this for inverters and static RAM wouldn’t be that helpful because a chip is a lot more than inverters and static RAM. Like I said, you would have to use some sort of passgate logic to make this make any sense.
And if we want to compare publications, here’s one of mine, specifically chosen due to its relevance to the Apple community - also, unlike this Arm article you cited, mine was peer-reviewed:
A 533-MHz BiCMOS superscalar RISC microprocessor
This 533-MHz BiCMOS very large scale integration (VLSI) implementation of the PowerPC architecture contains three pipelines and a large on-chip secondary cache to achieve a peak performance of 1600 MIPS. The 15 mm/spl times/10 mm die contains 2.7 M transistors (2M CMOS and 0.7 M bipolar) and...ieeexplore.ieee.org
(Some more at this link: https://ieeexplore.ieee.org/author/37341628900)
CMOS is generally understood as a design pattern whereby every "effective" transistor consists of a paired P and N transistor. The result of this pairing is substantially lower energy usage (think a mechanical system whereby everything that you want to move has an attached counterweight).
I'm out.
I tried to treat this interaction as one of learning, you seem intent on treating it as one of confrontation. Over what, I don't know, since stacked N/P transistors are coming, and they are being created for the same reason that side-by-side P/N transistors are used right now. Claiming that they're not "real" CMOS, whatever that means, won't stop their fabrication, their principles of operation, or the fact that people will call them CMOS.
Your beef seems to be some weird terminological thing that exists in your own mind but is invisible to an outsider. (Maybe you think CMOS = FET? I have no idea and little interest.)
1) What does your first sentence have to do with anything? Just because CMOS is “generally understood” to involve a paired N transistor and a paired P transistor doesn’t mean that the two (not 1!) transistor in the pair are *connected* to each other. And that is what the issue is with the 3D devices you are so fond of - they are ONLY useful for inverters (or circuits made of inverters - like SRAM) or pass gates, because those are the only structures that look like that.
2) ”counterweight?” What? That’s not how CMOS works. The way CMOS works is that you have current that would otherwise flow between VSS and VDD, and a channel connected path through N- and P-Fets to direct that current. If an input is a 1, it turns connected NFETs and shuts off connect PFETs. You arrange the P-Fets and N-Fets so that this current flow never happens (ideally). Instead, you either charge or discharge the output node.
3) Me disagreeing with your incorrect technical assertions is not a “confrontation.” You called me an ”internet rando.” I didn’t call you any names. I merely pointed out that I am also a published author in the art of circuit and CPU design.
4) I didn’t claim anything was no it “real” CMOS. I claimed it wasn’t CMOS at all. Because it is not. You presented a “CFET.” A CFET is NOT the same thing as CMOS. These are two completely different things.
I have a PhD in electrical engineering. I designed CPUs for a decade, including, for example, at AMD. I know what I am talking about. You are misinterpreting non-technical papers to mean things that they do not mean.
Right from the start you have been arguing against one thing after another that I never said.
I never said that the transistors are "connected" to each other. (Even aside from the issues of what "connected" means.)
And I put quotes around "transistor" because I was talking about "effective transistors".
What I said was:
[[
a CMOS "transistor" consists of two transistors, N and P. These can be stacked on top of each other instead of side by side.
- already in some situations the fundamental limit is no longer transistor size but the density of the wiring connecting to the transistors. This can be substantially helped by routing the "utility" connections (at first power/ground, later maybe clock) below the transistors rather than above
]]
This whole things seems built upon you insisting upon interpreting what I said in the most unreasonable way possible, up to and including inserting words that are not there.
And you seem determined to continue down this path, insisting that a CFET is not CMOS when every normal person speaks in exactly that way
The Complementary FET (CFET) for CMOS scaling beyond N3
The complementary FET (CFET) device consisting of a stacked n-type vertical sheet on a p-type fin is evaluated in a design-technology co-optimization (DTCO) framework. Through a double level access it offers a structural scaling of both standard cells (SDC) and SRAM by 50%. The proposed process...
I honestly don't know what's going on here. You seem determined to pick fights over language discrepancies that only you believe exist, seem determined to interpret analogies as concrete descriptive statements, seem determined to make up claims that simply aren't in the original text. This is not how most of us engage in discussion.