Sure, DMI is proprietary to Intel. I haven’t said otherwise so it hardly bears repeating (and it’s not particularly relevant). And yes, the T2 is connected via standard PCIe 3.0 lanes.
But the T2 doesn’t connect directly to the CPU. It connects to the PCH, as do a bunch of USB ports, WiFi, and other ports depending on the particular model of Mac, including GbE, SATA and even an SDXC slot in the case of iMac Pro.
There’s a ton of bandwidth available in the T2 on-chip; for instance recall two flash modules are connected to it. But all that I/O has to funnel down to the four PCIe lane-equivalent choke point that is DMI 3.0. Again, the T2 itself is not the limitation; the issue is the DMI connection.
If Apple wants to increase the bandwidth available to SSD storage, PCIe 4.0 is not necessary. Rather, dedicated PCIe lanes, assuming they are available, can be connected directly from the CPU itself to the T2, thus avoiding the bottleneck caused by congestion/saturation of an oversubscribed DMI bus.
re: A10=T2, I agree it’s extremely likely that Apple simply(!) added additional functionality to the A10 to create a dual-use SoC that can be utilized either in its original role in iOS devices or as the T2 for Macs. After all, transistors are cheap, additional pin-outs relatively so, and it’s an excellent way to leverage the design and manufacture of silicon that otherwise already exists.
But there’s no particular reason I can see to think T2s are plucked from parts not good enough for A10. For all we know, T2 are the highest bin; certainty relatively few are needed for that role in any case.