At Least One New MacBook With Apple Silicon 'Likely' at WWDC, Says Morgan Stanley Analyst

madebybela said:
so many products unveils rumored for this event (on top of all the software which is the main focus), at this point I'm having this gut feeling there actually wont be ANY hardware announcements lol
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Thats been said all this year every time there is a event. Its just as the year progresses, all these rumors get more out of hand. :D
 
One thing that I don't think many have considered is if they have two or three flavors of M1 chips that are available in all the Macs just like you can choose a Core - i5, i7, or i9 now. Maybe they do an M1 8-core, M1 10-core, and an M1 16-core. Each with corresponding graphics cores to match. Every year you have a new core design in lockstep with the A-series cores, but maybe it is always called the M1 or maybe it just iterates every year but without an X designation like the A-series did.
 
If they add mini led, pro motion, MagSafe and Face ID I'll be lining up at my nearest apple store straight after the event.
 
visualseed said:
There is really nothing to say they can't call these M1 as well. They can just be 16-Core (or more) variants. the X variants of the A series came out later and the only differences were the number of CPU/CPU cores. I would suspect a version number change would only come about after a change in design of the actual cpu/gpu/neural cores.

One of the things that I have noticed is that Apple advertisers the current M1 Macs as "8-core" which makes me believe this will be a significant point of differentiation in future products.
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Spoken like someone who doesn't understand any of the technical issues.

There are multiple dimensions along which the M1 is unsatisfactory for higher-end machines, and these are not easily fixed within the existing M1 framework:

- more cores (requires new masks, yes, but probably requires a lot more than that. Apple's current design clusters up to 4 performance cores as sharing a single L2. You probably don't want to scale that sharing beyond 4 cores or so. Which means the next design will probably replicate multiple of the 4-core+L2 clusters.
The good news is that Apple has already engaged in some of the work required by such a design, since the current designs already have a Performance cluster and an Efficiency cluster. But that's not all the work... There are issues like how the OS will schedule threads across these two performance clusters. There are technical issues like how interrupts will be routed across different clusters, or how TLB teardown will happen. It's not like these are impossible problems; but they are problems new to Apple, and one thing we have constantly seen with Apple is that rather than do things the "usual" way (which in the case of interrupts or TLB teardown, is really becoming a problem at large core numbers) they'd rather implement something completely new, which is risky but has paid off massively for them ever since the A6.

- more GPU.

- more RAM. Some aspects of more RAM are easy -- sure, you could reach 32GiB by putting two RAM chips on the other side of the SoC, or by putting them on the other side of the existing RAM chips (poor man's 3D stacking!) But there is the larger question of how do you want to support the truly large RAM footprints (1TB or more) desired by some Mac Pro customers? The obvious solution is a "minimal" RAM footprint directly on the package, plus expansion via something like CXL. But is that what they will choose? And of course that requires PCIe5 and a CXL controller designed into the SoC...

- more IO conectivity. Once again look at the grumbling about having only one "official" display connection and only two TB connections. People buying an iMac Pro/27" iMac will want at least 10G ethernet + 4TB + 4USB like they have right now.

- there is the basic question of how do you support a range from the demands of a macBook Pro up to a mac Pro (which might want about 4x the CPUs and GPUs of the macBook Pro), but do so at reasonable given that *all* these products together don't sell in very high volumes. The obvious answer is some sort of chiplet-type solution -- a baseline "M2X" chiplet, that can be cross-connected to one, two, or three other such chiplets. But once again now we're talking a completely different type of design; not just the packaging but the very basics of having connectivity (wiring points, and inter-chiplet communication protocol) between the chiplets, something that we've never seen on a prior Apple design.

The point is not that an M1 couldn't be redesigned to provide some of these (not all -- there's no PCIe5 and CXL on the M1, and replicating more of the PCIe4 lanes won't change that). It's that such a design makes little sense. Start with the newer better CPU (A15, with SVE/2 and ARM9), use a SoC design that's aimed at a "larger" product rather than sub-optimal modifications of a product with a different design target.
 
name99 said:
Spoken like someone who doesn't understand any of the technical issues.

There are multiple dimensions along which the M1 is unsatisfactory for higher-end machines, and these are not easily fixed within the existing M1 framework:

- more cores (requires new masks, yes, but probably requires a lot more than that. Apple's current design clusters up to 4 performance cores as sharing a single L2. You probably don't want to scale that sharing beyond 4 cores or so. Which means the next design will probably replicate multiple of the 4-core+L2 clusters.
The good news is that Apple has already engaged in some of the work required by such a design, since the current designs already have a Performance cluster and an Efficiency cluster. But that's not all the work... There are issues like how the OS will schedule threads across these two performance clusters. There are technical issues like how interrupts will be routed across different clusters, or how TLB teardown will happen. It's not like these are impossible problems; but they are problems new to Apple, and one thing we have constantly seen with Apple is that rather than do things the "usual" way (which in the case of interrupts or TLB teardown, is really becoming a problem at large core numbers) they'd rather implement something completely new, which is risky but has paid off massively for them ever since the A6.

- more GPU.

- more RAM. Some aspects of more RAM are easy -- sure, you could reach 32GiB by putting two RAM chips on the other side of the SoC, or by putting them on the other side of the existing RAM chips (poor man's 3D stacking!) But there is the larger question of how do you want to support the truly large RAM footprints (1TB or more) desired by some Mac Pro customers? The obvious solution is a "minimal" RAM footprint directly on the package, plus expansion via something like CXL. But is that what they will choose? And of course that requires PCIe5 and a CXL controller designed into the SoC...

- more IO conectivity. Once again look at the grumbling about having only one "official" display connection and only two TB connections. People buying an iMac Pro/27" iMac will want at least 10G ethernet + 4TB + 4USB like they have right now.

- there is the basic question of how do you support a range from the demands of a macBook Pro up to a mac Pro (which might want about 4x the CPUs and GPUs of the macBook Pro), but do so at reasonable given that *all* these products together don't sell in very high volumes. The obvious answer is some sort of chiplet-type solution -- a baseline "M2X" chiplet, that can be cross-connected to one, two, or three other such chiplets. But once again now we're talking a completely different type of design; not just the packaging but the very basics of having connectivity (wiring points, and inter-chiplet communication protocol) between the chiplets, something that we've never seen on a prior Apple design.

The point is not that an M1 couldn't be redesigned to provide some of these (not all -- there's no PCIe5 and CXL on the M1, and replicating more of the PCIe4 lanes won't change that). It's that such a design makes little sense. Start with the newer better CPU (A15, with SVE/2 and ARM9), use a SoC design that's aimed at a "larger" product rather than sub-optimal modifications of a product with a different design target.
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You tally missed my point but good to see your keyboard works.
 
at best i'd say a 16 inch high end new M? something with magsafe considering the invite clue of leopard which is about same time magsafe introduced, no 14

the 13 pro m1 doing to good why would they introduce 14 so soon, 14 won't be til 2022, but i hope i'm wrong
 
JPack said:
Then it would have been launched last year with the 13-inch Air and Pro. It makes zero sense.
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Also what doesn’t make sense is how they redesigned the base line iMac but not the base line pro… but here we are…

think about it saying then putting an M1 in the 16” would have been done last year with the 13” is the equivalent as saying them refreshing the design of the 16” makes no sense because they would have redesigned last years model already.

The one thing that makes me think we may not get a redesigned MBP this year is the Touch Bar still being present on the base MBP… it just seems weird to me that Apple will keep that only on the baseline pro and literally nothing else in the line up…
 
It could also be that we'll finally get a replacement for the rest of the 2018 Mac mini configurations, seeing as supply chain rumors seem to consistently fail at predicting new Mac mini launches more than literally any other Apple product.
 
If they annonce the new 16" model, will they remove the current Intel 16" model from the Apple Store immediately after?

I ask because I would like to update my 15" to latest Intel 16" (the next one if they offer a intel model or the current one otherwise). However, I'm afraid that if I wait too long, they could remove the current Intel 16" before I could order it.
 
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