IBM and 45nm Chip Development

[ksz]

You are right, up to a point. As dimensions became smaller the chips became more efficient, they used fewer electrons to store one bit or to change that bit's logic state. However, at around the 90nm level a new effect started to gain importance. For various reasons it became more difficult to isolate the various signals in the chip. What should be perfect insulators were now leaky insulators. Current flowing through a resistor generates heat. Any imperfection in the way materials are formed is magnified into a current leak.

Fantastic levels of genius and technology are being applied to this basket of problems. If they can come up with a break through to solve this leakage problem we'll see some spectacular products.

Agreed.

Gate leakage current (Ioff) is another significant factor (probably the most significant) for the 4x increase in dissipation power per generation. As transistors scale (i.e. de-magnify) from 180 to 90 to 65 to 45 to 30, both the gate length (Lg) and oxide thickness (Tox) drop. A shorter gate length allows a transistor to switch more quickly, but at 45nm, gate oxides are only about 5 atom widths deep. This oxide is designed to prevent current leakage from the active region back into the poly gate when the gate is turned off, but electrons jump the gate and induce a leakage current due to both (1) relatively poor dielectric property of the gate oxide and (2) narrow oxide depth. If the oxide depth is increased, more active or drive current is needed to switch on the gate, but the gate oxide will deliver better insulative properties. The ideal solution is to keep the gate oxide as thin as possible, but use or develop an oxide with a higher dielectric constant (high-k).

 

[vouder17]

I'll believe it when i see it

 

[GFLPraxis]

I'll believe it when i see it

What, you think it's unlikely that we'll reach 45nm by mid-2007? Sounds reasonable to me IMHO. It's not like "G5 PowerBooks next Tuesay!" rumors or anything. There are already 65 nm processors on the market (AMD I believe). Down from 90nm a few months ago. 45 nm two years from now does not sound unrealistic to me.

 

[dontmatter]

Reduces cost? Really? That's great, because I was under the impression (or maybe this impression is wrong) that shrinking doesn't just increase speed, it reduces power consumption and heat. Maybe apple will forget about the g5 PB, and wait for 2008 for a G6? heh.

Seriously, though, does size shrink power consumption, and how much?

Also, where is Intel in this? they workin on 65 or 45, or do we know?

 

[psycho bob]

Sooner or later the 45nm and below barrier will be broken. If it isn't all future technologies will come to a standstill. Computers have been a very accurate mark of technological and human advancement in the 20th/21st centuries. It is fair to say that in one form or another the world would be entirely different without the technologies that computers provide or the ones used to make computers.

If you had said 10 years ago that today we would be making chips using connections many many times smaller than a human hair and reaching the speeds we have you'd have been laughed at. Talking about 90nm technology 3 years ago would have thrown up many of the issues being discussed here with people saying it isn't going to happen.

The fact is technology like this goes far beyond simply benefitting the computer industry, the barriers will be broken. The thought of us as a race encountering a problem that couldn't be over come practically would be a significant and devastating first for mankind. While there are a number of things we can't do it is very rare that we come across an evolutionary problem in the technology sector that given time and money we cannot work around.

No chip maker is really leaping ahead anymore. Sure one might announce and ship something first but all are in the same ball park. Real advancement will only come if one maker can take a significant stride ahead of the rest for example a successful jump to 30nm by the end of the year. These things rarely happen if ever.

 

[psycho bob]

Reduces cost? Really? That's great, because I was under the impression (or maybe this impression is wrong) that shrinking doesn't just increase speed, it reduces power consumption and heat. Maybe apple will forget about the g5 PB, and wait for 2008 for a G6? heh.

Seriously, though, does size shrink power consumption, and how much?

If done right it can reduce power consumption. However as Intel found out with their first generation 90nm chips it can also generate more concentrated heat and use more power. As companies tend to increase clock speed upon reducing die size keeping power consumption the same would be acceptable. As people have stated here though there are a lot of question marks when doing something like this.

Only the scientists that work for the companies can ever really know what they are aiming for and what problems they'll encounter. If we all knew then we'd be making a mint and working with them not bashing out what we do know on a forum

One thing that is known though is that the smaller the die size the more concentrated the heat output. This is the reason the top G5's are water cooled, air cooling just isn't efficient. Sooner or later cooling will become the most important factor. How long I wonder before all PC's need liquid cooling? That would make a home brewed PC more interesting, you'd need to call a plumber

 

[GFLPraxis]

Reduces cost? Really? That's great, because I was under the impression (or maybe this impression is wrong) that shrinking doesn't just increase speed, it reduces power consumption and heat. Maybe apple will forget about the g5 PB, and wait for 2008 for a G6? heh.

Seriously, though, does size shrink power consumption, and how much?

Also, where is Intel in this? they workin on 65 or 45, or do we know?

Intel has 65 nm.
http://www.intel.com/pressroom/archive/releases/20040830net.htm

Hopefully Apple never even begun thinking about a G5 PB. Forget it. Everybody.

I'd much rather see e600 based PowerBooks. Dual core 1.5 GHz G4 at 25w or single core at 10w and 1.5 GHz, scales to 2 GHz. Incredible battery life and great speed.

http://www.freescale.com/webapp/sps/site/overview.jsp?nodeId=02VS0l72156402

Then there's the e700, up to 3 GHz and 64-bit (this is a G4 ), but thats way off. The e600 should be available very soon IIRC. Perhaps this is the big surprise for WWDC? 1.5 GHz G4 iBooks that use a mere 10w, giving it great battery life, and dual core PowerBooks?

 

[jnicolso1]

Does any one know if the use of diamond rather than silicon as the insulator will improve the performance of chips as the shrick the size. I seem to remember an article about using diamond wafers. Obviously you need large synthetic diamonds but I think that technolgy has or is being developed.

 

[cube]

Seems IBM may have been just trying to keep in the news, this is from http://www.forbes.com/markets/feeds/afx/2005/05/26/afx2060330.html

This 45nm collaboration is old news.

 

[G.Kirby]

I hope they can get it right. And by that time the current chips should be blistering. A lot can happen between now and 2007. Intel, cell, multicore and so on.

 

[Abstract]

Agreed.

Gate leakage current (Ioff) is another significant factor (probably the most significant) for the 4x increase in dissipation power per generation. As transistors scale (i.e. de-magnify) from 180 to 90 to 65 to 45 to 30, both the gate length (Lg) and oxide thickness (Tox) drop. A shorter gate length allows a transistor to switch more quickly, but at 45nm, gate oxides are only about 5 atom widths deep. This oxide is designed to prevent current leakage from the active region back into the poly gate when the gate is turned off, but electrons jump the gate and induce a leakage current due to both (1) relatively poor dielectric property of the gate oxide and (2) narrow oxide depth. If the oxide depth is increased, more active or drive current is needed to switch on the gate, but the gate oxide will deliver better insulative properties. The ideal solution is to keep the gate oxide as thin as possible, but use or develop an oxide with a higher dielectric constant (high-k).

As someone who clearly knows less than you (understatement of the year ), I always that while less heat was being produced if you scale down smaller (ie: 13nm to 9 nm to 6.5nm), less heat was being generated, but since everything else is smaller as well, the density of the heat on the chip actually became greater, so the chip is actually hotter now than before, which is why the new G5s require liquid cooling. So yes, less heat is being produced on todays chip but the heat density (I guess it would be Joules/cm^3 or something) is higher, so a better cooling method is needed.

 

[BenRoethig]

The new Dual 2.9999999 GHz G5 Tower....... Almost...... so close

With the same chipset and Radeon 9675 graphics.

 

[AidenShaw]

IBM uses PPC in only one server - its slowest

While there is no mention of PPC chips in this article, I would think that IBM would definately steer towards PPC with this technology as their fastest servers are PPC based.

Hardly - IBM uses POWER5, Xeon and Opteron chips in their fastest servers.

Only one server uses a PowerPC (the JS20 has a 2.2GHz PPC970), and it benchmarks as the slowest server in the current IBM lineup. The HS20 (same server with a Xeon) is about 60% faster than the JS20 (www.specbench.org)

SPECint  SPECfp    Model
-------  ------    ----------------------------
 1040     1241     JS20 (2.2 GHz PPC970)
 1260     2236     p5 510 (1.65 GHz POWER5)
 1584     1771     e326 (2.4 GHz Opteron)
 1701     1777     HS20 (3.6 GHz Xeon 64-bit)

 

[Lurch_Mojoff]

If IBM are to stick to the punch with Moor's Law, this means they'll be able to produce 65nm chips this summer. Right?

 

[Rustus Maximus]

I don't even want to think how hot these things will get.

Well how did you think they were going to cremate those 15 clowns we were speaking about earlier?

 

[XForge]

actually, i think that is more like saying "so we are going to get 15 clowns in this toolbox instead."

....what is scary, is i bet they do it!

Clowns are highly malleable.

 

[zelmo]

Might work if you cremate the 15 clowns first.

That approach might raise some other problems though.

I bet the G5 PowerBook generates just about enough heat to make this happen...

 

[VanMac]

It's called the 2.7GHz G5, but there's a 10% error in the manufacturing process apparently.

So, taking the error margin to the high end, we are still only at 2.97GHz

 

[SPUY767]

Hardly - IBM uses POWER5, Xeon and Opteron chips in their fastest servers.

Only one server uses a PowerPC (the JS20 has a 2.2GHz PPC970), and it benchmarks as the slowest server in the current IBM lineup. The HS20 (same server with a Xeon) is about 60% faster than the JS20 (www.specbench.org)

SPECint  SPECfp    Model
-------  ------    ----------------------------
 1040     1241     JS20 (2.2 GHz PPC970)
 1260     2236     p5 510 (1.65 GHz POWER5)
 1584     1771     e326 (2.4 GHz Opteron)
 1701     1777     HS20 (3.6 GHz Xeon 64-bit)

The POWER5 is a PPC chip. And SPEC benchmarks typically give crappy ratings on the RISC side of the fence. I will note the FP score of the Power5 tho.

 

[iGary]

I am on the rope with Lacero with this.

Yes there are many ways to cool electronic items, including R-134a compressed refrigerant, peltier (sp?) devices, and other ways to bring temps below room temperature. But how cost effective are these, and how much impact will it play on keeping computers small, light and quiet?

Granted more items are in the works, and new items are invented every day, but I doubt we will se processors like this in our PC's in the next 2 years, at 3+ GHZ.

Just my thoughts, nothing more.

Pfft.

Not expensive at all, just put your new Nuclear Mac™ G5 into one of these:

 

[dagger01]

You guys make my head hurt...

I want to address some comments in this thread.

First, the 90nm fab difficulties that IBM experienced are typical with all the 90nm fabs. Yields are always low during the first three years of a new process. The reason why the yield problems have had a greater effect on the PPC 970 than the Intel chips is that Intel has three (or more by now) 90nm fabs worldwide, IBM has one in Fishkill, NY. That one fab is also doing more than just churning out PPC 970s. IBM fabs chips for other manufacturers, like AMD.

Second, voltage leakage at 90nm has been a particular problem and was a main contributor to the delay of Intel's Prescott line of processors and the 2.3GHz PPC 970. The voltage leakage causes thermal issues that also contribute to low yields. It's other technologies like strained silicon and silicon on insulator that deal with the voltage problems and related thermal issues with these denser processes.

Third, 65nm is not being skipped for 45nm. The 65nm process is still valuable and will be put into production soon by IBM. The 45nm move is probably related to multi-core processors, the Cell processor, and/or related to laptop capable G5s. This is all conjecture at this point, but makes sense based on where things are and where things are going.

Finally, we'll see 3.0+ GHz soon enough. Besides, it's not how fast you go, but how efficient you are with the clock cycles. Intel played the MHz game an is now paying for it. The PPC 9XX line has got a lot of legs in it, don't worry about the stuck-at-X GHZ-for-a-year problem. There are other ways of getting more performance out of the processor than bumping the clock speed; adding instruction units and multiple cores being the most obvious. AMD has the edge right now with the dual-core Opteron, but that won't last very long.

Good stuff is around the corner. Patience will be rewarded in spades!

 

[cube]

AMD is doing well with their 90nm process.

 

[dagger01]

The POWER5 is a PPC chip. And SPEC benchmarks typically give crappy ratings on the RISC side of the fence. I will note the FP score of the Power5 tho.

Uhhh...that's backwards. The PowerPC line of processors are derivatives of the POWER architecture. They share the same instruction sets, but are designed differently.

Benchmarks are relevant to the type of application they represent. SPEC means more to one set of people as Linpack means something to another set, and POV and Photoshop mean something to others. Benchmarks are relative. Gauge your choice of processor on its performance in your application domain and use the corresponding benchmarks to decide.

 

[AidenShaw]

The POWER5 is a PPC chip.

http://www-03.ibm.com/chips/products/powerpc/rdmap/

Why then isn't POWER described in the IBM PowerPC roadmap?

IBM's engineering and marketing are pretty distinct at putting POWER and PowerPC into different camps. Even though the family label "PowerPC" sometimes is applied to both - there are real differences between the two product families.

(For example, POWER chips don't support little-endian modes, whereas the PowerPC Book E architecture supports both little and big endian modes.)

 

[AidenShaw]

Uhhh...that's backwards. The PowerPC line of processors are derivatives of the POWER architecture. They share the same instruction sets, but are designed differently.

Yes, the POWER architecture was first, then the PowerPC architecture was defined.

Most CPUs labeled as PowerPC (IBM750,Freescale,...) were designed as PowerPC chips to the latter architecture.

Newer POWER chips follow most of the rules in the PowerPC architecture, so that by and large they're pretty compatible.

The PowerPC 970 chip is a unique bastard design. Most of the chip is a simplified POWER4 (a dual-core chip), with AltiVec and some other PowerPC stuff "welded" on.

The POWER4 heritage of the PPC970 is readily visible in its appetite for electricity....