Smaller process also means lower per-chip costs because you can get more on the same wafer.
Alternately you can fill the die area with other logic or cache and keep the price roughly the same.
I'm guessing we'll see the later, though the extra logic/cache will mean higher leakage current.
Anyone know details on the Power5 power reduction techniques? If they're just turning off the clock it seems there will be less of a benefit as leakage goes up... Are they gating power to the various sections yet? Seems like this would also have limited benefit if you've got to cycle power at a GHz rate...
)
