I reread my post and realized I'm in error: I stated that the power requirements are "not linear" with frequency. You and others trying to give me a basic course in Physics are correct. Dynamic power requirements (capacitance charging) are linear with frequency and the square of core voltage. For some reason I was thinking of leakage current without considering that it would just shift the y-intercept and not in a manner favorable to my argument!
Your computation assumes that the 970 drains 0 Watts at 0 frequency and creates a generous estimation of the power requirements at the same core voltage for lower clock speeds. This is incorrect. There is a static power drain: a constant subthreshold current (leakage power) in a transistor. This can be quite significant. For instance, the 3.2Ghz P4 leakage is around 20 Watts(!) at any clock speed--enough to power a G4 or suck a laptop battery dry!
Intel solves this in the P4M by applying SpeedStep to power down or clock down when idle (or just generically when on battery power). However the real savings is much simpler. Core voltage needs to be kept high to allow fast switching and core voltage is quadratic in dynamic power and exponential in static power. This effect gets exemplified in the Pentium M/Banias by clocking even slower and getting a better return--the PM has a leakage of < 1W. Too bad the sequel 90nm Pentium M/Dothan leaks like a sieve (10W).
So yeah, you're mostly right but you are assuming that a 90nm 970 will need to be at the same voltage. That assumption is usually erroneous--it's really hard to say here since you are comparing a 1.6Ghz part to a 2.0Ghz one. Usually the core voltage would be lower in a notebook than a desktop and thus the power is significantly lower. In fact most low power chips implement Dynamic Voltage Frequency Scaling (the generic term for Intel "SpeedStep" or AMD "PowerNow") which scale the frequency and voltage for processor demand.
I think in the interest of completness there should be another power drain due to the finite voltage response of the transistor. I don't know if this is significant since I'm not a hardware guy.
So I should be comparing them at the same clock speed? Hmm, then the P4 must really suck because its performance per clock is so miserable. We should ditch them and dig up our old Pentium 3's
If I'm going to go through this absurdity, why don't I compare different generations of the same CPU to skew things back in my direction? For instance your middle of the line 55W @ 2Ghz P4/Northwood used to drain 75W when it was a 2Ghz P4 Williamette (Again this is due to a drop in core voltage from 1.75 to 1.5V made possible by moving from 180nm to 130nm: to give you a rough feeling how significant core voltage can be and what a die shrink enables).
The reason they have similar power requirements at the same clock is because they have similar transistor counts (and core voltage)--power being an absolute linear with transistor count (and thus exponential with time due to Moore's Law which is why we're in this mess: the days of the 6W max power G4 are gone forever).
I've not seen anyone consider a 2Ghz P4 in the same class as a 2Ghz G5. Nobody benchmarks this because we all know the answer. They compare the P4 at 3.2Ghz or, more appropriately the P4 Xeon at 3.06Ghz (Intel claims 82 watts for both).
I say "Intel claims" because all the above are Intel "thermal guidelines". In reality the P4 3.2Ghz peaks above 100W as I mentioned earlier. Compare peak to peak and average to average. A single 3.2Ghz P4 uses more power than two 2.0Ghz G5s!
