Originally posted by hitman
Can anyone answer my question though :
Which is better for overall performance, a larger L3 cache or a faster system bus?
I'll take a crack at it.
For big jobs such as rendering large 2D animations that require hours and hours of processing, the faster bus is far more beneficial. In fact. L3 would not offer any signficiant benefit.
For small jobs, particularly many small jobs, such as web browsing, email, M$ Office, and others apps running simultaneously with blocks of data smaller aggregately than the size of the L3 cache, then the L3 cache kicks butt over the faster bus (33 MHz delta for the bus versus an L3 to CPU bus that is typically 500 MHz or so...much faster than main bus).
So, large L3 and L2 cache, benefits all operations that are small enough to place most or all of its data into the cache for quick computation when the CPU's need it. But, if you're rendering or doing something on blocks of data that far exceed the L2 and L3 cache, then you're dependent upon the front side bus.
This is why many posters are expressing dismay over the new PowerMacs. Because, the throughput from the system controller to the CPU's is 1.3 GB/s, up from 1.05 GB/s. Well, this is still a good speed bump for large jobs. You're essentially gettting a 33% (roughly) improvement on large jobs because of the larger throughput from main memory to the CPU's.
Many of us had hoped that Motorola would have re-worked the CPU's so that they could take in far more throughput. Afterall, if you only have 1.3 GB/s of throughput from main memory to CPU's for big jobs, the 18 GLOPS of super duper potential aint gonna happen. The faster CPU's and the large L2 and L3 cache will give us a snappier response.
I seriously question the benefit and value of faster CPU's. I don't regard 'snappier response' as a truly practical offering. I see faster overall data throughput from main memory to CPU's to results (computation) as the ideal metric, as opposed to "real world" performance.
Here's a block diagram from macteens.com to illustrate: