Originally posted by John Q Public
...where to begin...
Processor Bus (aka: Front Side Bus) only dictates Processor to "North-Bridge" of the motherboard's chipset.
Memory Bus is what the traces running from the Memory Hub/Controller (usually part of the "Northbridge" of the system's controller chipset)
you do know that most current chipset designs don't use the traditional Northbridge/Southbridge design philosophy anymore, right? P4 doesn't. The latest G4s don't. The G5 doesn't.
Here's a quote from a PC Tech site to illustrate
"The 820 chipset employs the Accelerated Hub Architecture that is offered in all Intel 800 series chipsets - the first chipset architecture tomove away from the traditional Northbridge /Southbridge design."
System Bus is NOT 800, 900, or 1000Mz.
.... er, sorry, it is 800MHz.
The HyperTransport protocol integrates thePower Mac G5s I/O subsystems and connectsthem to the system controller. Serial ATA, GigabitEthernet, FireWire, USB 2.0 and optical digital andanalog audio are all integrated through twobidirectional 16-bit, 800MHz HyperTransportinterconnects for a maximum throughput of 3.2GBper second. The system bus connects components with 800MHz HT busses. They have half the bandwidth of the processor busses as they are only 16 bit instead of 32bit.
Memory Bus: Partially determined by type of memory used DDR speed ratings are a misnomer...the actual speed is half the rating because of latency issues. Which is why PC2100 (DDR266) speeds are roughly equivalent to PC133 SDRAM...PC3200 is actually equivalent to 200Mz considering the archetecture.
You aren't helping your stance that you know what you are talking about.
a) the actual speed is half the DDR speed not because of latency, but because that's the actual speed.
b) ddr speeds are NOT equivilent to SDR speeds. There is a reason to use DDR over SDR, the effective bandwidth IS double what you get in SDR.
c) The latency IS generally higher in ticks, but that doesn't mean that the latency is longer in real time. If the memory controller would take 1 second (just for clear argument) to fetch an instruction.. the reasoning is, it will take twice as many ticks to get the data with DDR as SDR because with DDR there are twice as many ticks in a second. BUT, it still takes one second.
... and, you should probably be a little more clear when you discuss memory speed. Are you refering to frequency, bandwidth, latency? they are all different things.
NOW we get to the System Bus...speeds on the system bus are limited to what they are connceted to.
ISA=8Mz
EISA=16Mz
PCI=33Mz
PCI (Enhanced)=66Mz (which was used on second generation G3's and Yikes G4 for video)
AGP=66Mz (it doesn't matter which flavor 1/2/4/8x...it's only 66Mz...where the differences in AGP formats resides...the width of the data path and how the Northbridge saturates the bus)
PCI-X=133Mz (although PCI-X has been out for nearly 2 years on Workstations and Servers, as a replacement for the aging PCI (Enhanced), there is still not adequate support...and unfortunately won't be until "Mainstream" PC manufacturers begin to build it into their systems...as a sidebar...the next generation of Video Card will be PCI-X because it allows higher bandwidth than the proposed AGP 16x)
why is most of this relevent? ISA and EISA? HUH? who gives a crap? EISA didn't even make it on the PC.
And I'm not going to muddy the waters further with NuBus, Micro-Channel or VESA...
don't worry, you've done a good job of that already.
back to your points above...
PCI-X isn't mainstream yet, but it is completely compatible with PCI. Compatability and the fact that these are considered 'pro' machines are the reason why Apple went PCI-X. There are PCI-Express devices out now, but generally they are only running on PCI-X because they _actually_ need the bandwidth. By putting PCI-X into the G5s, Apple has not only extended the useable life of the chipset, but they've also prepped the machine for the use of high end interface cards like GigE, FibreChannel, Myrinet...
Another point. Could you provide some backup to your contention that newer AGP ports are actually only run at 66MHz? I was always under the impression that an AGP 4x slot actually ticked off at 266 million cycles per second.
...to wrap...a CPU is an expensive calculator and it crunches numbers increasingly faster each generation...but to do its job, relies on components to perform optimally...there has been no machine produced since the first generation PPC's or Pentium (and clones) where the Processor and memory bus performed in parallel...likewise the System Bus in and of its components hasn't performed in parallel with the processor since 68030 and 80386...Likewise...the G5 is not using a Gz speed memory or system bus...although it's processors can each speak to the north-bridge at up to 1Gz (thus the Dual-FSB)...it's still the System Bus Chipset that allocates instructions to every other part of the system...the processor is the brain...but the System Bus is the Central Nervous System.
huh?
the first pentiums ran on 60 and 66MHz sys buses... only the first two (complete crap) models ran on a 1:1 ratio. The first PPC chips ran at 1:2 from the start. My Powermac 6100/66 had a 33MHz system bus. There has NEVER been a PPC that ran at a 1:1 cpu to system multiple.
The G5 is not using GHz memory, but it is using 400MHz memory on a 128 bit bus. The processors (in the 1.8GHz for example) run on two, one way, 32 bit 900MHz buses. The effective bandwidth of the 1.8 GHz processor bus is essentially equal to the memory bus (due to routing overhead on the HT BASED processor bus). And, because of the one way, 32 bit nature of the processor buses... the CPU can actually only read data at half the rate of the memory (same with exclusive writes).
and yes...I did find your accusation of a lack of knowledge exceedingly rude...
I don't like name calling (unless the person is REALLY an idiot and they just keep coming ;-)
I'm not sure you've put up a good rebuff for that other person's slam yet though.