interesting, can you post a picture from Gauge Pro in classic Mac OS for me? 
(do cmd d for extra details IIRC)
(do cmd d for extra details IIRC)
0
L2E
L2 enable. Enables L2 cache operation (including snooping) starting with the next transaction the L2 cache unit receives. Before enabling the L2 cache, the L2 clock must be con gured through L2CR[2CLK], and the L2 DLL must stabilize (see the hardware speci cations). All other L2CR bits must be set appropriately. The L2 cache may need to be invalidated globally.
2–3
L2SIZ
L2 size—Should be set according to the size of the L2 data RAMs used. A 256-Kbyte L2 cache requires a data RAM con gur ation of 32 Kbytes x 64 bits; a 512-Kbyte L2 cache requires a
con gur ation of 64 Kbyte x 64 bits; a 1-Mbyte L2 cache requires a con gur ation of 128K x 64 bits. 00 Reserved
01 256 Kbyte 10 512 Kbyte 11 1 Mbyte
4–6
L2CLK
L2 clock ratio (core-to-L2 frequency divider). Speci es the cloc k divider ratio based from the core clock frequency that the L2 data RAM interface is to operate at. When these bits are cleared, the L2 clock is stopped and the on-chip DLL for the L2 interface is disabled. For nonzero values, the processor generates the L2 clock and the on-chip DLL is enabled. After the L2 clock ratio is chosen, the DLL must stabilize before the L2 interface can be enabled. (See the hardware speci cations). The resulting L2 clock frequency cannot be slower than the clock frequency of the 60x bus interface.
000 L2 clock and DLL disabled 001 ÷1
010 ÷1.5
011 Reserved
100 ÷2
101 ÷2.5
110 ÷3
111 Reserved
7–8
L2RAM
L2 RAM type—Con gures the L2 RAM interf ace for the type of synchronous SRAMs used:
• Flow-through (register-buffer) synchronous burst SRAMs that clock addresses in and o w data out • Pipelined (register-register) synchronous burst SRAMs that clock addresses in and clock data out • Late-write synchronous SRAMs, for which the MPC750 requires a pipelined (register-register)
con gur ation. Late-write RAMs require write data to be valid on the cycle after WE is asserted,
rather than on the same cycle as the write enable as with traditional burst RAMs.
For burst RAM selections, the MPC750 does not burst data into the L2 cache; it generates an address for each access. Pipelined SRAMs may be used for all L2 clock modes. Note that o w-through SRAMs can be used only for L2 clock modes divide-by-2 or slower (divide-by-1 and divide-by-1.5 not allowed). 00 Flow-through (register-buffer) synchronous burst SRAM
01 Reserved
10 Pipelined (register-register) synchronous burst SRAM
11 Pipelined (register-register) synchronous late-write SRAM
LBF asked me how I verified L2 was working...here's an interesting picture showing the system profiler, Sonnet metronome and Powerlogix profiler. System profile doesn't show my 1MB cache though.View attachment 1728695
Question for LightBulbFun,
LBF, From a technical standpoint, is there anything preventing me from loading 10.5 on this 9650 using your img and xpostfacto? I understand I have a G3/500 processor but other than it being slow, anything else you can think of?
This thread is from 2006 and refers to a beta of Leopard. Early betas (e.g. 9A241) will run on a G3 but later betas and the final release won't.
awesome to see you around still!Hey,
Great thread on the 9600 and 10.5 with G4s.
Just to add some potentially helpful info here is a 9600 booting in 2008as part of Mac Mod work
https://web.archive.org/web/20130924163750/http://www.mactech.com/2008/09/23/leopard-pre-agp
However, so great that all this extra work has gone on to sort out L2 cache and various foibles of the 9600.
PM8500 is also possible if of any interest.
Someday I'll get the 9600 setup again.
If anyone has a broken 9600 I'd be interested as have a 9700 motherboard which needs a permanent setup, rather than swapping it with a 9600 motherboard.
If you boot using verbose mode then we should be be able to see where early on in the process it's hanging.Hey guys. For years, I was dreaming of a fully maxed out Power Mac 9600 that is capable of running Leopard. I am halfway of achieving that dream. My 9600 has an 800MHz G4, 1.25GB of RAM, Radeon 9200, ATA133 card, FW/USB, and a 10/100 Ethernet card.
I am writing to you guys because I cannot get 10.5.8 to work on my 9600 and even my Molar Mac. The newest Leopard I was able to get working is 10.5.2. After 10.5.3, my beige machines refuse to boot up to those Leopard versions. I make sure it has all the modified extensions and everything. But I get a stuck Apple logo on bootup and the spinning wheel does not appear. It’s just a stuck Apple logo on a gray background.
I tried using LightBulbFun’s 10.5.8 restore image with Disk Utility and the same issue happens. Stuck Apple logo on a gray background and no spinning wheel. I made sure to use Xpostfacto and initiate the install everything command to the 10.5.8 partition.
What could I possibly be doing wrong here? 10.5.2 only works for me, but I really would love to have the latest version of Leopard.
Any advice?
Yes, glad you picked up on that... Had also spotted that there were nvram patches.... But never got round to it.awesome to see you around still!
indeed I used your awesome work as a jumping off point to get Leopard onto my Various OWR macs, at some point I need to reivist this work and see if I can put together a better image
(id really like to see if I can get something working with the stock 10.5.8 kernel rather then having to roll back to 10.5.5's kernel)
awesome to hear you got a 9700 Motherboard, I would love to play with one of those some day, even see if I can get OS X running one
curiously apple did make an NVRAMRC patch and Platform expert kext for the 9700 for OS X! which is included in xpostfacto, but I dont think anyone has ever actually tested it
Good question... Will get back to youWhat type of ram did the six slot 9700 prototype use?
Did it have an ATA controller?
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Power Macintosh 9700
The Power Macintosh 9700, code named "Power Express", was a high-end prototype tower system from Apple Computer. Prototype specimens that leaked from Apple contained 6 PCI slots, a DVD-ROM drive, and what is believed to be an engineering sample of an early PowerPC G3 processor, code named...apple.fandom.com