Re: Re: Re: Re: Re: It's not a G5 people, this isn't SpyMac...
Yes, the G4 can address 64GB of memory. Unfortunately 32bit addresses make this difficult. The OS would need to internally represent every memory location as 64bit, causing significant performance reduction and resident system memory bloat. The Xeon is able to accomplish 36bit addressing in a slightly more graceful way due to the x86's segmented memory model. This effectively involves bank switching - the OS running on a Xeon can only utilise 4GB of memory at a time, but can swap banks (with a performance penalty) in order to effectively increase the addressable memory size.
Yes and no. PPC970 represents individual instructions in a simpler manner, utilising a concept similar to the P4's crack and decode method to product micro-ops. The internal state of the PPC970 is much more complex than existing G4 designs.
This is not exactly true. Both CPUs can run very efficiently once code is cached in their individual L3's. What causes most of the performance problems in the duals is keeping the caches coherent between the CPUs. Memory traffic is a secondary concern. Remember that memory runs at 133MHz while the CPUs runs at 1GHz+. On a similar note: the reason why we have not seen quad G4 workstations is because the G4 IPC Bus (Inter Processor Communication) performs poorly when more than two processors are connected to it. The PPC970 fixes this problem.
I congratulate the Apple Engineer(s) who routed the 970's 900MHz FSB on the upcoming apple mobos.
I believe the G4 can natively address 64 GB of memory.
Yes, the G4 can address 64GB of memory. Unfortunately 32bit addresses make this difficult. The OS would need to internally represent every memory location as 64bit, causing significant performance reduction and resident system memory bloat. The Xeon is able to accomplish 36bit addressing in a slightly more graceful way due to the x86's segmented memory model. This effectively involves bank switching - the OS running on a Xeon can only utilise 4GB of memory at a time, but can swap banks (with a performance penalty) in order to effectively increase the addressable memory size.
Are these examples of the simpler design?
Yes and no. PPC970 represents individual instructions in a simpler manner, utilising a concept similar to the P4's crack and decode method to product micro-ops. The internal state of the PPC970 is much more complex than existing G4 designs.
The PowerMac G4s that are currently on the market make very little use of the second processor due to its insanely slow system bus--167MHz, and not nearly enough.
This is not exactly true. Both CPUs can run very efficiently once code is cached in their individual L3's. What causes most of the performance problems in the duals is keeping the caches coherent between the CPUs. Memory traffic is a secondary concern. Remember that memory runs at 133MHz while the CPUs runs at 1GHz+. On a similar note: the reason why we have not seen quad G4 workstations is because the G4 IPC Bus (Inter Processor Communication) performs poorly when more than two processors are connected to it. The PPC970 fixes this problem.
I congratulate the Apple Engineer(s) who routed the 970's 900MHz FSB on the upcoming apple mobos.