I don't think this is true. Ice Lake W (if released) will almost certainly use socket 4189. I'm not sure there are any historical examples of memory channels increasing without pin counts. If there was a 3647 variant it was probably a very early engineering sample, I think.
Just because the Memory channels are there on the die doesn't mean Intel has to hook them up to pins.
For the max sized die ( XCC ) with 38-40 cores they probably also need the larger package size for better thermals. However, for the 'low core count" ( LCC) dies they could just skip the 2 memory controllers being hooked up and just more to higher base clocks on the smaller boards space.
They didn't do it with memory channel pins before but I think they did this with UPI I/O in the past. Using the same die for multiple products. Downsiding the I/O to "lower" die into a more affordable price segment.
At the point where in the same 8-20 core count as the W3200 is the two extra memory controllers going to make a huge difference to their implementation given a bump in RAM clock speeds ?
Moving from 6 to 8 channels is so the additional cores don't 'starve' waiting on data when under max memory bisection bandwidth loads. If have 12+ more less cores that "max pressure" is going to be lower.
The problem with cranking up to the bigger package is that soak up more board space. ATX boards are only so big. 3497 is already heavily on the "large" size. More DIMMs also soak up more board space. At some point likely to end up with less general purpose PCI-e slots . In the "enthusiast" market that can be 'bad' becauase more slots is "more power".