So aux0 is maybe the laptop's built-in display?
What's the "extra set of dp_aux"? What do you mean "Two monitors"? What are the two monitors connected to?
I don't know where you got the hex string from. You have everything beyond byte 16 as 00 but the bin file has non-zero values. Did you use different methods of reading the DPCD to generate the hex string and the bin file?
Suggests an MST hub with HBR3 x2 input and HBR2 x4 output. MST hubs are good for converting fast/narrow input to slow/wide output like a PCIe switch does.
HBR3 x2 6 bpc RGB or 4:4:4 allows pixel clock up to 720 MHz (1440p169 CVT-RB). But 6 bpc is poor color depth - you'll see banding unless there's a lot of dithering.
It has these 1440p modes:
144Hz 604.250 MHz
120Hz 497.750 MHz
100Hz 410.500 MHz
60Hz 241.500 MHz
It says max dotclock 600 MHz but the 144Hz mode exceeds that. I guess this max dot clock is ignored and maybe you can get up to 720 MHz.
600 MHz is the max dot clock for HDMI (assuming 4:4:4 8bpc).
There's no mention of 4:2:0 support. What version of DP is the display set at? I wonder if the EDID changes if you change the DisplayPort version? The EDID of the HDMI port of the display will be different for sure.
Assuming no DSC and no 4:2:0, DP 1.1 can do 480 MHz with 6bpc 4:4:4 or 540 MHz with 8bpc 4:2:2 - both have 144Hz out of range but 4:2:2 should allow 120Hz.
The DPCD suggests the hub does not support DSC. Does that mean the hub cannot pass DSC unchanged?
I made a dumpdpcd command in my AllRez project on GitHub which can parse the DPCD data that is dumped to a binary file.
Code:
dpcd = {
00000h: 12 14 c2 81 01 19 01 81 38 2d 04 00 00 00 82 00 // ........8-......
00080h: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00100h: 1e 82 00 02 02 00 00 10 01 00 00 00 00 00 00 00 // ................
00200h: 41 00 77 00 01 03 22 00 00 00 00 00 00 00 00 00 // A.w...".........
00210h: 00 80 00 80 00 00 00 00 00 00 00 00 00 00 00 00 // ................
00240h: 00 00 00 00 00 00 20 00 00 00 00 00 00 00 00 00 // ...... .........
00300h: 00 00 1a 38 16 00 00 00 00 11 00 00 00 00 00 00 // ...8............
00500h: 00 e0 4c 44 70 31 2e 34 00 10 82 01 00 00 00 00 // ..LDp1.4........
00510h: 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // (...............
00600h: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
02000h: 00 00 41 00 00 00 00 00 00 00 00 00 77 00 01 03 // ..A.........w...
02200h: 14 1e c2 81 01 19 01 81 38 2d 04 00 00 00 82 00 // ........8-......
02210h: 08 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................
03000h: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 // ................
03030h: 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 // ................
68000h: 85 65 ed 4a 93 00 00 00 00 00 00 00 00 00 00 00 // .e.J............
68020h: 00 00 00 00 00 00 00 00 03 00 00 00 00 00 00 00 // ................
69000h: 00 00 00 00 00 00 00 00 00 00 00 24 a2 3c 6d 6f // ...........$.<mo
69010h: c6 b6 5e 51 03 77 59 de 3b f0 80 06 54 ee 1a c5 // ..^Q.wY.;...T...
69020h: 8e 56 54 63 38 1b 47 a1 8b 82 c8 2f f8 c5 d4 f4 // .VTc8.G..../....
Receiver Capability
00000h DPCD_REV: 1.2
00001h MAX_LINK_RATE: HBR2
00002h MAX_LANE_COUNT: 2, ENHANCED_FRAME_CAP, TPS3_SUPPORTED
00003h MAX_DOWNSPREAD: MAX_DOWNSPREAD_0_5, TPS4_SUPPORTED
00004h NORP: 2
00005h DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT, PORT_TYPE = DisplayPort, FORMAT_CONVERSION, DETAILED_CAP_INFO_AVAILABLE
00006h MAIN_LINK_CHANNEL_CODING: CAP_ANSI_8B10B
00007h DOWN_STREAM_PORT_COUNT: 1, OUI_SUPPORT
00008h RECEIVE_PORT_0_CAP_0: ?0x38
00009h RECEIVE_PORT_0_BUFFER_SIZE: 1472 bytes per lane
0000ah RECEIVE_PORT_1_CAP_0: ASSOCIATED_TO_PRECEDING_PORT
0000eh TRAINING_AUX_RD_INTERVAL: 8ms all, EXTENDED_RECEIVER_CAP_FIELD_PRESENT
00080h DOWNSTREAM_PORT_0: PORT_TYPE = DisplayPort, HPD aware
Link Configuration
00100h LINK_BW_SET: HBR3
00101h LANE_COUNT_SET: 2, ENHANCED_FRAME_EN
00103h TRAINING_LANE0_SET: TRAIN_VOLTAGE_SWING_LEVEL_2, TRAIN_PRE_EMPH_LEVEL_0
00104h TRAINING_LANE1_SET: TRAIN_VOLTAGE_SWING_LEVEL_2, TRAIN_PRE_EMPH_LEVEL_0
00105h TRAINING_LANE2_SET: TRAIN_VOLTAGE_SWING_LEVEL_0, TRAIN_PRE_EMPH_LEVEL_0
00106h TRAINING_LANE3_SET: TRAIN_VOLTAGE_SWING_LEVEL_0, TRAIN_PRE_EMPH_LEVEL_0
00107h DOWNSPREAD_CTRL: SPREAD_AMP_0_5
00108h MAIN_LINK_CHANNEL_CODING_SET: SET_ANSI_8B10B
Link/Sink Device Status
00200h SINK_COUNT: 1, SINK_CP_READY
00202h LANE0_1_STATUS: LANE0 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
00202h LANE0_1_STATUS: LANE1 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
00203h LANE2_3_STATUS: LANE2 =
00203h LANE2_3_STATUS: LANE3 =
00204h LANE_ALIGN_STATUS_UPDATED: INTERLANE_ALIGN_DONE
00205h SINK_STATUS: RECEIVE_PORT_0_STATUS, RECEIVE_PORT_1_STATUS
00206h ADJUST_REQUEST_LANE0_1: LANE0 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0
00206h ADJUST_REQUEST_LANE0_1: LANE1 = ADJUST_VOLTAGE_SWING_LEVEL_2, ADJUST_PRE_EMPHASIS_LEVEL_0
00207h ADJUST_REQUEST_LANE2_3: LANE2 = ADJUST_VOLTAGE_SWING_LEVEL_0, ADJUST_PRE_EMPHASIS_LEVEL_0
00207h ADJUST_REQUEST_LANE2_3: LANE3 = ADJUST_VOLTAGE_SWING_LEVEL_0, ADJUST_PRE_EMPHASIS_LEVEL_0
00210h SYMBOL_ERROR_COUNT_LANE0: 0, valid
00212h SYMBOL_ERROR_COUNT_LANE1: 0, valid
00214h SYMBOL_ERROR_COUNT_LANE2: 0
00216h SYMBOL_ERROR_COUNT_LANE3: 0
Automated Testing Sub-Field
00246h TEST_SINK_MISC: TST_CRC_COUNT = 0, TEST_CRC_SUPPORTED
Source Device-Specific
00300h SOURCE_OUI: 00-00-1A = ADVANCED MICRO DEVICES
00303h SOURCE_ID: 38 16 00 00 00 00 // 8.....
00309h SOURCE_HW_REV: 1.1
Branch Device-Specific
00500h BRANCH_OUI: 00-E0-4C = REALTEK SEMICONDUCTOR CORP.
00503h BRANCH_ID: 44 70 31 2e 34 00 // Dp1.4.
00509h BRANCH_HW_REV: 1.0
0050ah BRANCH_SW_REV: 130.1
00510h : 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // (...............
Sink Control
00600h SET_POWER: SET_POWER_D0
DPRX ESI (Event Status Indicator)
02002h SINK_COUNT_ESI: 1, SINK_CP_READY
0200ch LANE0_1_STATUS_ESI: LANE0 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
0200ch LANE0_1_STATUS_ESI: LANE1 = CR_DONE, CHANNEL_EQ_DONE, SYMBOL_LOCKED
0200dh LANE2_3_STATUS_ESI: LANE2 =
0200dh LANE2_3_STATUS_ESI: LANE3 =
0200eh LANE_ALIGN_STATUS_UPDATED_ESI: INTERLANE_ALIGN_DONE
0200fh SINK_STATUS_ESI: RECEIVE_PORT_0_STATUS, RECEIVE_PORT_1_STATUS
Extended Receiver Capability
02200h DP13_DPCD_REV: 1.4
02201h MAX_LINK_RATE: HBR3
02202h MAX_LANE_COUNT: 2, ENHANCED_FRAME_CAP, TPS3_SUPPORTED
02203h MAX_DOWNSPREAD: MAX_DOWNSPREAD_0_5, TPS4_SUPPORTED
02204h NORP: 2
02205h DOWNSTREAMPORT_PRESENT: DWN_STRM_PORT_PRESENT, PORT_TYPE = DisplayPort, FORMAT_CONVERSION, DETAILED_CAP_INFO_AVAILABLE
02206h MAIN_LINK_CHANNEL_CODING: CAP_ANSI_8B10B
02207h DOWN_STREAM_PORT_COUNT: 1, OUI_SUPPORT
02208h RECEIVE_PORT_0_CAP_0: ?0x38
02209h RECEIVE_PORT_0_BUFFER_SIZE: 1472 bytes per lane
0220ah RECEIVE_PORT_1_CAP_0: ASSOCIATED_TO_PRECEDING_PORT
0220eh TRAINING_AUX_RD_INTERVAL: 8ms all, EXTENDED_RECEIVER_CAP_FIELD_PRESENT
02210h DPRX_FEATURE_ENUMERATION_LIST: VSC_SDP_EXT_FOR_COLORIMETRY_SUPPORTED
PCON HDMI CONFIG PPS Override Buffer
0300fh CEC_LOGICAL_ADDRESS_MASK_2: CEC_LOGICAL_ADDRESS_15
03030h : 00 00 00 00 03 00 // ......
HDCP 1.3 and HDCP 2.2
68000h AUX_HDCP_BKSV: 85 65 ed 4a 93 // .e.J.
68028h AUX_HDCP_BCAPS: BCAPS_HDCP_CAPABLE, BCAPS_REPEATER_PRESENT
DP HDCP 2.2 Parameters
6900bh HDCP_2_2_REG_CERT_RX: 24 a2 3c 6d 6f // $.<mo
69010h : c6 b6 5e 51 03 77 59 de 3b f0 80 06 54 ee 1a c5 // ..^Q.wY.;...T...
69020h : 8e 56 54 63 38 1b 47 a1 8b 82 c8 2f f8 c5 d4 f4 // .VTc8.G..../....
69030h : 59 7d bc 5e a8 47 e1 50 5a 74 50 fe 82 71 c6 03 // Y}.^.G.PZtP..q..
69040h : 53 bd 4a 55 02 cd 32 84 9a 22 11 5a 3c 0f 41 bd // S.JU..2..".Z<.A.
69050h : 7a 5f 88 76 11 3f 95 02 cc e2 35 7e d2 93 a2 d7 // z_.v.?....5~....
69060h : 23 df b5 0a 89 47 d0 8d 50 07 b5 61 31 3d 23 54 // #....G..P..a1=#T
69070h : 32 e1 77 90 67 18 a3 5a f0 5a f9 d4 16 f2 28 41 // 2.w.g..Z.Z....(A
69080h : 25 57 32 9a a5 c5 49 65 14 f7 0a 61 cc 64 56 49 // %W2...Ie...a.dVI
69090h : 01 00 01 10 00 84 8a c1 a1 1c 0a c5 5d 9a ca 25 // ............]..%
690a0h : f0 ee 09 91 14 c8 c1 e9 49 7d 1a 9e a5 a6 ea 71 // ........I}.....q
690b0h : 30 31 29 d0 e1 53 05 67 30 d7 33 7e d3 54 16 90 // 01)..S.g0.3~.T..
690c0h : c7 5e 68 07 98 83 c8 86 26 ec 0c 9d 38 d0 7d b9 // .^h.....&...8.}.
690d0h : 84 a8 65 e9 ec ff d3 e9 1b 6b f5 ac bf 01 68 30 // ..e......k....h0
690e0h : 91 93 6e 6c 93 85 d3 15 9a 11 43 b9 5b a7 e3 07 // ..nl......C.[...
690f0h : 18 a1 bf 6c 45 64 f5 22 44 55 84 15 22 4a 13 59 // ...lEd."DU.."J.Y
69100h : d9 06 4f f5 be 5f ef 48 aa 9b 4d a4 f0 a7 cc 67 // ..O.._.H..M....g
69110h : fd 06 99 74 2f 65 40 90 01 5a 9d b6 87 bc 98 77 // ...t/e@..Z.....w
69120h : dd 61 81 37 10 f3 23 b4 72 df 87 df 2b 9d 05 86 // .a.7..#.r...+...
69130h : 79 2d 32 6d b0 d0 dc 9d 2f 6a 04 65 79 eb 0a 45 // y-2m..../j.ey..E
69140h : 18 73 3e 85 d4 30 72 8a 3b 31 56 1d f5 c4 79 81 // .s>..0r.;1V...y.
69150h : 14 e2 a6 fd a4 80 42 36 90 94 35 26 5b 7c e7 98 // ......B6..5&[|..
69160h : 20 62 48 c6 35 f1 6b 8c bb 40 fd 7a 6a 31 31 da // bH.5.k..@.zj11.
69170h : 50 dd bc 29 fb 14 38 16 7c f9 e0 82 4a 55 fd 48 // P..)..8.|...JU.H
69180h : 28 0f 98 b9 92 8a 12 31 fc 91 a4 ea 8b 30 07 1d // (......1.....0..
69190h : 15 b1 c3 8e 51 58 cf 6e bf b6 85 2b 41 07 cc b0 // ....QX.n...+A...
691a0h : f8 c1 19 1c be 30 9f 55 91 89 c4 fe b0 2e dc 3f // .....0.U.......?
691b0h : 2a c3 f3 a2 ac dc 9f d0 a0 e4 2e f3 12 29 b2 70 // *............).p
691c0h : 53 05 4e 42 2a 82 9e b7 98 67 62 4c 64 cb 66 85 // S.NB*....gbLd.f.
691d0h : 11 1a c8 93 12 89 2c 1b 9b 02 21 17 a7 34 ef 1a // ......,...!..4..
691e0h : 15 da 52 fe be c5 73 c7 8d e9 60 bd 93 7e d4 11 // ..R...s...`..~..
691f0h : e9 7a 61 9c c6 fc d6 bd 9b b5 8d 54 9d 8c 73 e5 // .za........T..s.
69200h : c1 bc b1 6d 13 99 e5 d4 c1 0a 42 49 00 5f e7 f4 // ...m......BI._..
69210h : 0c bb 41 35 fd // ..A5.
6921dh HDCP_2_2_REG_RX_CAPS: VERSION = 2, RECEIVER_CAPABILITY_MASK = 0, HDCP_CAPABLE, REPEATER
Undefined
ffff0h : 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 80 // ................
}; // dpcd
You see that there's no DSC info in this dump (its all zeros). Here's some of the important parts:
LINK_BW_SET: HBR3
LANE_COUNT_SET: 2
DOWN_STREAM_PORT_COUNT: 1
DOWNSTREAM_PORT_0: PORT_TYPE = DisplayPort
SINK_COUNT: 1
SOURCE_OUI: 00-00-1A = ADVANCED MICRO DEVICES
<-- your graphics card
BRANCH_OUI: 00-E0-4C = REALTEK SEMHICONDUCTOR CORP.
<-- the MST hub? Don't know what model or why there's only one downstream port.
You can get DPCD info for the display if it is connected to the laptop instead of the MST hub of your USB-C dock.
Linux doesn't expose dp aux channel devices for getting DPCD from downstream ports of MST hubs directly? I suppose you need to daisy chain some MST hubs to be sure.
It may be possible to send sideband messages to the dp aux device to access DPCD from downstream MST ports indirectly but that's a little more complicated.
Basically, you create a request for some bytes of the downstream DPCD (the request includes a path to navigate the MST hub topology), write the request to some bytes in the DPCD of the first device, and get a response.
My AllRez app does that. Maybe its code can be converted to a unix shell script (if you don't want to find a linux api to do it in a C app).