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70% boost in logic??? That is going to be insane if they take advantage of the neural engine for those chips. Very excited for the devices a year/two years from now with that.
"Up to 70%" is the key part.

N3 should be good, but maybe not that good over N5.
 
When it reaches 0nm technology, does the chip physically disappear? :)
I believe the definition of atom is "the smallest unit of a chemical element that still exhibits the characteristics of that element". I don't know if it's achievable, but once you get to the size of a silicon atom that's the theoretical limit; below that size, you lose the behavior of silicon. So, it won't physically disappear but at atomic sizes IMO the chip will start to behave erratically (i.e., they're already starting to see CPU instability at current feature sizes).
 
IBM is actually ahead of them, they are on 2nm.

IBM announced 7nm in 2015. They always announce it earlier. In case you wonder how they did with the 7nm.


Making it in a lab is nothing compare to making them in factories for these guys.
 
I believe the definition of atom is "the smallest unit of a chemical element that still exhibits the characteristics of that element". I don't know if it's achievable, but once you get to the size of a silicon atom that's the theoretical limit; below that size, you lose the behavior of silicon. So, it won't physically disappear but at atomic sizes IMO the chip will start to behave erratically (i.e., they're already starting to see CPU instability at current feature sizes).

Nobody is seeing CPU instability. And since the size of the transistor has nothing to do with the node size, we aren’t particularly close yet to their being an insurmountable issue with quantum tunneling. Right now, we’ve switched to 3D transistor gate structures to allow an more consistent electric field to enable the transistors to fully turn off (thus preventing static leakage current). There are new gate structures on the roadmap over the next few years that will prevent leakage even as the transistors get smaller.

And once we reach the threshold where the size is such that the transistors cannot be turned off, there are multiple other solutions (for example, compound semiconductors with heterojunctions, different transistor types such as HBTs that rely on vertical distances instead of horizontal, etc.)
 
IBM is actually ahead of them, they are on 2nm.

IBM is not a foundry. They do cutting edge research yes, but that's a completely different kettle of fish.

TSMC provides foundry services for mass production for the mainstream. What that article press release outlines is 2 nm technology that could be adopted for mass production several years from now... which is about the same time TSMC is expected to go 2 nm.

 
TSMC must be using some sort of alien technology to stay on ahead of everyone. /s

Now if only they can work on scaling up the production facilities to meet the growing global chip shortage.
 
One naive (and probably dumb) question: Why was it not possible to go from 10nm directly to 5nm? Why do the iterations have to be that "small"?
 
Will pick up an iMac 32 inch when this gets implemented. But I will wait 6 months after launch though so I can save on it, because we all know there will be discounts going into 2023. But then, I might wait on the enhanced 3NM process that will launch in late 2023. Then again, might as well just upgrade to 1 NM and get the best bang for my buck. Sigh.
 
One naive (and probably dumb) question: Why was it not possible to go from 10nm directly to 5nm? Why do the iterations have to be that "small"?

They don’t have to.

But it’s hard work to create the machines that you need to make things “a little bit smaller” and to make the EDA software tools that you need to make sure that the products actually work, etc. So we eke out a little bit of improvement each year.
 
IBM is actually ahead of them, they are on 2nm.

2nm. Pfft.

TSMC laughs at IBM's 2nm chip


 
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