Become a MacRumors Supporter for $50/year with no ads, ability to filter front page stories, and private forums.
TSMC must be using some sort of alien technology to stay on ahead of everyone. /s

Now if only they can work on scaling up the production facilities to meet the growing global chip shortage.
Or they have good marketing guys who claim this process is 3nm when it isn't.

I know the Intel hate runs strong here but TSMC does not have a magical fab technology a decade ahead of Intel. They're not far off in real production capabilities. Intel's upcoming 7nm should be comparable with what TSMC calls 3nm.

Theyre just marketing terms, not actual measurements.
 
Last edited:
Well, I bet there are people who haven't switched to Apple Silicon yet due to limited RAM sizes they offer. I'm one of them - waiting for larger RAM...
ofc but from that pic we couldn't figure out if the ram was an issue, just the Cpu temp :)
 
So, again in late 2022 Apple will be the first to bring 3nm ..since 80% of TSMC production per year is reserved for Apple until 2024
 
Absolutely amazing the speed at which these processors are evolving. We will be at 1NM before we know it
 
  • Like
Reactions: peanuts_of_pathos
Looking forward to it. Excited news 😆
Im not. With the current chip shortage, the last thing we need is new production node which means more defects and lower yield. TSMC is already 10 years ahead of Intel and Samsung. They should first meet demand, then improve IMO.
 
  • Like
Reactions: TakeshimaIslands
Taiwan’s innovation in semiconductor production in recent years is just NUTS. I literally cannot fathom a 3nm scale… Well done TSMC
 
Article is not correct - it's either 15% speed gain OR 30% less power. Never both - people always seem to confuse this.
Maybe they went for both? They could have opted on this new fab to not squeeze more transistors on and instead slightly scale it back for more performance and energy savings
 
IBM is actually ahead of them, they are on 2nm.

i bet TSMC has a 2nm in the lab also for some time...but, not like IBM, they dont take credits for 1 SoC..but they prefer to take credits with bringing 3nm next year for millions of devices that users can actually take advantage of
 
  • Like
Reactions: peanuts_of_pathos
I wonder if we'll see sub 1nm process within a decade.
Yes we will but only in the process names. TSMC is already at 3nm and they release new processes every year. If they stick with the naming convention then we will be under 1nm in just three years. However, keep in mind that nowadays the name has very little to do with silicon feature sizes. So, in physical terms, we are nowhere near sub 1nm process.
 
Maybe they went for both? They could have opted on this new fab to not squeeze more transistors on and instead slightly scale it back for more performance and energy savings
yes this is what M1 it is, its the definition of more power whiles saving power
 
  • Like
Reactions: no_idea
I wonder if we'll see sub 1nm process within a decade.
Yes. TSMCs nm figures are not the same as how people used to think of them. It’s as much marketing as it is anything else. I.e 1nm TSMC will probably be possible without any crazy graphene or other futuristic technology.
 
Or they have good marketing guys who claim this process is 3nm when it isn't.

I know the Intel hate runs strong here but TSMC does not have a magical fab technology a decade ahead of Intel. They're not far off in real production capabilities. Intel's upcoming 7nm should be comparable with what TSMC calls 3nm.

Theyre just marketing terms, not actual measurements.

Except that’s not true. Intel’s 7nm design rules are similar to TSMC’s 5nm design rules, not TSMC’s 3nm design rules.
 
Article is not correct - it's either 15% speed gain OR 30% less power. Never both - people always seem to confuse this.

Actually you are incorrect.

When you reduce the node size, you can decrease the size of transistors and wires. Doing so allows you to decrease the transistor gate capacitances and the interconnect parasitic capacitances. Decreasing capacitance increases speed and decreases power. First, power is decreased because power is a linear function of capacitance. (It is also a linear frequency of switching frequency, but more on that in a moment).

Second, speed is increased because the time it takes to charge or discharge a wire and a transistor gate is a function of current, and current is a linear function of capacitance. (It is also a linear function of voltage).

So you have a lot of choices here. You can keep frequency and voltage the same, and then get a 40-45% power reduction. You can ramp up the clock by 15% and get a 30’ish% power improvement. You can increase the voltage and get more speed at the same power. You can decrease voltage and get a huge power improvement at the same speed. etc. etc.
 
If only the 3nm process actually had 3nm transistors. It's only marketing unfortunately, no feature on the wafer is actually 3nm.
Why is that bad? It means there's plenty of room left for FURTHER miniaturization...
 
Register on MacRumors! This sidebar will go away, and you'll see fewer ads.