Re: Re: The Whole Package
Originally posted by Rincewind42
No flames, just a little counter logic. There are really only two things holding the G5 back from a PowerBook. CPU power usage, and System controller power usage.
What will it take to reduce both? They can do it with process shrinks (90 nm due by end of the year, prolly see both chips hitting machines by march) or speed drops.
Personally, I wouldn't be surprised if Apple implemented both to get a G5 in the PowerBooks by summer 2004.
A 1.6Ghz G5 running on a 533Mhz system controller would accept DDR 333 ram without the need to dual channel (the G5 running on a 533 Mhz FSB would only be able to shuffle about 2100 MB/s in either direction, 600 MB/s less than DDR 333 can do).
Similarly a 2Ghz G5 running on a 667 controller would push 2700 MB/s in either direction. We already have DDR 333, so that's not new to PowerBooks.
I would further expect them to implement an 8-bit hyper transport bus to link the rest of the systems to the controller. Unlike the PowerMac, the PowerBook doesn't have PCI slots to feed, so the 16-bit hyper transport+slots go away. I don't know the power usage statistics on Hypertransport, but I doubt that they are a deal breaker.
And it wouldn't surprising that the PowerBook would use a slower FSB than the PowerMac - they traditionally have had a 1 generation behind FSB anyway.
Finally, with the PowerBooks not using dual cpus and having fewer system resources to use bandwidth on the motherboard, they can do away with a lot of the power consumers and bandwidth requirements that the PowerMac has. No, they won't be as fast as the desktops, but they will be faster than what we have today.
Hey, good to see your posts again!
One minor and one major comment...
Minor: the PBs have DDR333, but even though Apple keeps talking about reading data on both edges, I think they're only using one stroke of the data and certainly not running them full speed through the slower G4 bus...
So the memory in the current PBs will pull less power than if it was running full tilt with a G5.
Major: I still can't judge how the G5 will perform if you throttle it's bus... Your suggestions would reduce the front side bus speed, then go to single channel DDR so you can't hide the memory latencies any more.
Granted, going to 90nm would almost certainly include increasing the L2 cache size to probably 1MB, but I don't know if that's enough.
The new G4s have 512KB, which seems to be enough to do without the L3, at least on some benchmarks, but the G5 design would be built expecting a main memory bus between 4 and 10 times as fast...
I'm growing increasingly enamored with the idea of maintaining two processor families-- one for desktops and one for portables. That way IBM could stay focused on optimizing the 970 for high speed desktops and their own servers, and a portable chip could be optimized for performance per mW...
At this point, I guess I don't care much. It doesn't look like Apple is going to do anything rash, so whatever they choose to do should be well designed...
