If it really is the same process with different "branding," why is the Samsung chip 10% smaller as expected?... Finfet designs which TSMC calls 16nm and Samsung calls 14nm
lol. cause he/she doesnt have one. probably wrote this message hiding from his/her basement and thinking its a witty commentWhere did you get an iPhone 7 from bro?
"... two identical Apple iPhone 6S phones contained two different A9 chips. The smaller is branded APL0898 and is manufactured using Samsung's 14nm Technology."ok retards,
APL0898 - 6S 14nm Samsung
APL1022 - 6S+ 16nm TSMC
please cry till its confirmed tomorrow.
If it really is the same process with different "branding," why is the Samsung chip 10% smaller as expected?
As expected based on math and physics - the same design on 14nm will be smaller than 16nm. A 105mm2 layout produced with a 16nm process will be closer to 95mm2 with a 14nm process. See https://en.wikipedia.org/wiki/Die_shrink for more.As expected to what?
40% faster than what? Not Samsung's 14nm Finfet design.If you look up statistics TSMC touted there 16nm Finfet+ design is 40% faster with the 55% efficiency which will be followed up with their 10nm tech.
So maybe I missed something. Where was it confirmed that the tsmc chip caused overheating and battery issues?
I will agree that Samsung has more expertise in building refrigerators, and in copying TVs and vacuum cleaners.we have to agree that samsung has more expertise in building hardware
"... shrinking a die reduces the current used by each transistor switching on or off in semiconductor devices while maintaining the same clock frequency of a chip, making a product with less power consumption (and thus less heat production)"chances are, power consumption of both the chips are pretty similar. i actually hope i get the tsmc chip when i buy my phone. it will run cooler.
Hang on.. But we all hate Samsung don't we.. ? LolAnd I'm sure majority of people, including myself, would like to know they received the version with the Samsung chip...
Any way to check what version you have without doing a teardown?
As expected based on math and physics - the same design on 14nm will be smaller than 16nm. A 105mm2 design in 16nm will be closer to 95mm2 in 14nm. See https://en.wikipedia.org/wiki/Die_shrink for more.
40% faster than what? Not Samsung's 14nm Finfet design.
You must be kidding. Tell that to nVidia: http://www.extremetech.com/computin...y-with-tsmc-claims-22nm-essentially-worthlessBut everyone in the industry knows is that for semiconductors, TSMC is absolutely the number one.
"... shrinking a die reduces the current used by each transistor switching on or off in semiconductor devices while maintaining the same clock frequency of a chip, making a product with less power consumption (and thus less heat production)"
https://en.wikipedia.org/wiki/Die_shrink
You must be kidding. Tell that to nVidia: http://www.extremetech.com/computin...y-with-tsmc-claims-22nm-essentially-worthless
There are four fabs that can produce the 14nm Samsung Finfets: Samsung has three, two for mass production and one for prototyping while there is only one run by Globalfoundries.Samsungs 14nm Finfet design which also got contracted out to global foundries was rated about 30% faster and 25% more efficient than samsungs 28nm tech.
TSMC stated there 16nm Finfet design is 30% faster and 25% more efficient than their 28nm tech and their Finfet+ is up to 40% faster and 55% more efficient than their 20nm SoC or 65% faster and 70% more efficient than their 28hpm tech
Seriously? That many people read MacRumors or other tech sites and will be concerned about this? Jeezus people just enjoy your devices and stop looking for problems!
There are four fabs that can produce the 14nm Samsung Finfets: Samsung has three, two for mass production and one for prototyping while there is only one run by Globalfoundries.
Those performance numbers are meaningless. Which designs does each correlate to?
And I'm sure majority of people, including myself, would like to know they received the version with the Samsung chip...
The scaling in die size matches the scaling in fabrication nodes.assuming both chips 1) are optimised for space (do u know they use same packaging? or pads? there is a good chance that the die size is larger to improve yield for TSMC 2) uses the same convention defining their finfet fab processes.
I'm even more sure that the VAST majority of normal people won't give a monkey's. Very few of us obsess that way.